With the introduction of microprocessor-based relays, a low-cost Fast Bus Tripping Scheme can be implemented to provide a fast and selective solution for faults on distribution buses. The scheme consists of microprocessor-based overcurrent relays installed for each feeder and for each main supply. Fast Bus Tripping Scheme is designed to speed up clearing time for a distribution bus fault with a resultant decrease in the arc flash hazard. This paper elaborates a Fast Bus Tripping Scheme design example for three sections of the distribution buses under all operating scenarios, presents key considerations identified during design practice from different perspectives, such as CT connection arrangement, applied protection functionalities, relay time coordination and relay communication methods. Recommendations have been provided accordingly.

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