140 / 1971-01-01 00:00:00

Double-tail Comparator With Reduced Delay Time For Low Supply Voltage In 90nm Technology

5182,5183,5184,5185

A quantitative delay analysis of a double-tail dynamic comparator is presented. The facts that impact the delay of the double-tail comparator are investigated, and the time of decision delay is analyzed. Based on the analysis, delay time can be reduced theoretically and a new dynamic comparator is proposed. Also the analysis demonstrates that the proposed comparator is more efficient for low supply voltage. All the analysis results are verified by post-layout simulation. The proposed comparator is realized in 90nm CMOS technology, and a conventional comparator is realized for comparison.