Current and emerging systems are deployed with heterogeneous architectures and accelerators of more than one type e.g. GPGPU, Intel® Xeon PhiT, FPGA along with hybrid processors of both lightweight and heavyweight cores (e.g APU, big.LITTLE). Such architectures also comprise of hybrid memory systems equipped with stacked/hierarchical memory and non-volatile memory in addition to regular DRAM. Programming such a system can be a real challenge along with locality, scheduling, load balancing, concurrency and so on.

This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems.

The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.