Driven by the needs of future multi-processor server architectures that support flexible highly adaptive energy-efficient high-performance computing, the main challenge considered in this workshop is to design high-performance, rate-adaptive, and energy-efficient communication architectures between the individual processors on different boards. To enable high data rates of up to 100 Gbit/s, we consider carrier frequencies in the range of 180 GHz to 300 GHz and a transmission bandwidth of 30 GHz. Such high carrier frequencies pose many challenging technological problems across all levels of the transceiver design, ranging from the required semiconductor technology, over circuit design of the radio frequency front-end up to the digital baseband. The high carrier frequency poses challenging requirements for the underlying process technology as operating frequencies up to 300 GHz are required. The design of the radio front-end is challenging due to the high carrier frequency as well as due to the required energy efficiency. Quantization with low bit rates, low latency channel coding, and analog beamforming are concepts relevant to the physical layer design. In the higher-level communication architecture, compute nodes are assumed to consist of 3D stacked processor chips with thousands of cores and local memory offering massive intra-node parallelism. This leads to multi-flow multi-hop concurrent communication within the computing platform and to several interesting design challenges regarding forward, routing, network coding, and many more. The workshop will bring together academic researchers and industrial professionals to identify and discuss technical challenges and recent results related to Broadband Wireless Communication between Computer Boards. Position papers, technology overviews, and case studies are also welcome.