To keep pace with the performance increase predicted by Moore's Law, homogeneous/heterogeneous processor aggregates have been extensively adopted both at the High Performance Computing (HPC) and at the embedded system domains. However, such steadily increase (often attained by simply scaling the number of computing cores within a chip) has been threatened by several architectural and technological constraints: limited parallelization opportunities (either at data, task, or even at instruction level); reduced memory throughput and complex cache hierarchies; limited communication bandwidth; thermal, power and energy constraints, etc. On the other hand, the prevailing heterogeneous computing architectures, often integrating different types of coprocessors (e.g., Intel Xeon Phi) and accelerator components (e.g., GPUs, FPGAs, etc.) has introduced complex challenges to efficiently program and implement HPC applications. On the embedded domain, different compromises to cope with strict energy efficiency requirements have been demanded. Despite the several different approaches that have been considered either at the processor architecture level (e.g., ARM big.LITTLE clusters) or at the coprocessor/accelerator level (e.g., mobile GPUs, reconfigurable SoCs, etc.), complex challenges are still posed in order to attain the ever increasing performance levels that have also been claimed in this specific domain. Therefore, it is widely recognized that next generation HPC and embedded systems can only benefit from the hardware’s full potential if both processor and architecture features are taken into account at all development stages - from the early algorithmic design to the final implementation stage.