Symposium III: Dry &Wet Etch and Cleaning

Advanced FEOL etching 
- Polysilicon/ metal/ high-k gate stack etching, gate first and replacement gate integration schemes
- 3Dgate stack etching for FinFET, tri-gate device
- Spacer etching
- CD and LER/LWR control

Advanced interconnect etching, MOL/BEOL etching
- Contact, CA and self-aligned CA patterning and etching
- Etching of low-k dielectric materials
- Low-k and ultra low-k trench-via patterning, mask opening, CD, profile control, damage cleaning
- Self-aligned via (SAV) etching for metal hardmask dual-damascene scheme.
- LWR control

Etching challenges for advanced 193nm immersion lithography and advanced double exposures and double etching integrations
- Advanced photo resist trimming and etching
- Etching challenges for tri-layer mask integration schemes

Interactions of plasma and other treatments with photoresists
- The fundamentals of surface interactions of plasmas and photoresists
- Advanced photoresist treatment for the enhancement of pattern transferring

Plasma Processing for 3D Integration, TSV and MEMS/NMES

Advanced memory etching and patterning
- Advanced memory materials
- DRAM, eDRAM, Flash memory 
- Advanced nonvolatile memory, such as MRAM, PCM, and other new memory devices

Advanced plasma sources and process control

Photo resist stripping and clean

Post plasma treatment cleaning

Wet etching and cleaning